(a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a MOSFET formed in an inherent region as well as a CMOSFET formed in well regions of a semiconductor substrate.
(b) Description of the Related Art
Some CMOSFET semiconductor devices are comprised of two MOSFETs formed in a P-well and an N-well of a semiconductor substrate, respectively, and a MOSFET formed in an inherent region of the same semiconductor substrate.
In the specification and the claims, the inherent region is defined as a region for forming a MOSFET, extending within the semiconductor substrate and having the same type of conductivity and the same impurity concentration as the semiconductor substrate. Further, the MOSFET formed in the inherent region is termed an undoped MOSFET for convenience hereinafter.
FIG. 1 is a sectional view of a conventional CMOSFET semiconductor device including an undoped MOSFET. As shown in FIG. 1, a P-well 51 for forming a MOSFET, an N-well 52 for forming another MOSFET, and an inherent region 53 for forming an undoped MOSFET are provided adjacent to each other under and including a main surface of a P-type semiconductor substrate 41.
A field oxide film 44 is selectively formed on the main surface of the semiconductor substrate 41 to separate the P-well 51, the N-well 52, and the inherent region 53 from each other. An N.sup.+ diffused-layer 49 is formed in the P-well 51 and the inherent region 53, and P.sup.+ diffused-layer 50 is formed in the N-well 52, respectively to provide source/drain regions.
In a P-type region just under the field oxide film 44, a P.sup.+ -type impurity layer 46 having a high impurity-concentration is formed as a channel stopper. A gate oxide film 47 and a gate electrode 48 thereon are provided on the main surface of the semiconductor substrate 41 for each of the MOSFETs.
The method of forming the undoped MOSFET will now be described with reference to FIGS. 2(a)-2(d) showing a sectional view of the undoped MOSFET in each process step.
First, as shown in FIG. 2(a), an oxide film 42 and then a nitride film 48 are formed on the surface of the inherent region 53 in the P-type semiconductor substrate 41. Then, the oxide film 42 and the nitride film 43 are patterned by means of a photolithographic technique and an etching technique so as to mask the inherent region 53. Next, as shown in FIG. 2(b), boron B.sup.+ ions are implanted to form a P.sup.+ -type impurity layer 46. Then, as shown in FIG. 2(c), a field oxide film 44 is formed on the P.sup.+ -type impurity layer 46 by a thermal oxidation method.
In the next step, as shown in FIG. 2(d), after removing the nitride film 43 and then the oxide film 42, the gate oxide film 47 and the gate electrode 48 are formed by patterning. Then, arsenic As.sup.+ ions are implanted, by using the gate oxide film 47 and gate electrode 48 as a mask, thereby forming N.sup.+ diffused-layers 49 to provide source and drain regions with the inherent region.
According to the prior art illustrated in FIG. 1 and FIGS. 2(a)-2(d), the field oxide film 44 and the P.sup.+ -type impurity layer 46 are intended to perform element-to-element isolation for the undoped MOSFET.
By the way, in order to integrate elements or circuits with high integration density in a CMOSFET semiconductor device having such an undoped MOSFET as mentioned above, it is preferred to shorten the distance between the N.sup.+ diffused-layer and the N-well region adjacent thereto.
However, when it is attempted to shorten the distance in the conventional CMOSFET semiconductor device mentioned above, it causes a problem that when the undoped MOSFET is activated, a punch-through is likely to occur between the N.sup.+ diffused-layers of the undoped MOSFET and the N-well region adjacent thereto, resulting in that leakage current flowing into the N-well region remarkably increases.